1. Technical Field
The present invention relates generally to complementary metal-oxide semiconductor (CMOS) chip manufacturing, and in particular, to the process area for forming ohmic contacts to devices using self-aligning silicide (salicide) processing.
2. Related Art
Formation of ohmic contacts to devices using self-aligning silicide (silicide) processing is a common semiconductor fabrication step. During this process, it is oftentimes advantageous to form silicide a p-type structure such as a field effect transistor (PFET), and not an n-type structure such as an NFET. Typically, however, selectively siliciding p+ silicon (Si) material requires additional blocking photomask levels, which adds many steps to the process and thus adds complexity.
In one approach, disclosed in U.S. Pat. No. 5,342,798 to Huang, selective salicidation of source/drain regions of a transistor is performed by implanting into a first set of source/drain (S/D) regions to increase a doping density thereof. All source/drain regions are then annealed to form to oxidization regions; a thinner oxidation region is formed over the first set of S/D regions. A metal layer is then formed over the oxidation regions and annealed to form metal-silicide over only the thinner oxidation region. The unreacted metal is then stripped. Since this approach requires an implant and anneal step, the process is greatly complicated. In addition, the selectiveness of this approach does not delineate between n-type and p-type structures, which limits its applicability.
In view of the foregoing, there is a need in the art for a way to selectively silicide p-type structures and not n-type structures.